CSMC provide accurate and validated PDKs to our mutual customers for fast time-to-market by maximizing design productivity. These process packages consist of all the necessary components to design, simulate, layout, and verify a chip design, including schematic symbols, device Models, technology files, parameterized cells (pcells), physical verification decks(DRC/LVS/LPE), etc.
Packaged design documents | PDH(process design handbook) | Process outline | |
---|---|---|---|
Application note | |||
Layout Rule | |||
Electrical Design Rule | |||
PCM Spedfication | |||
Mask Tooling Table | |||
SPICE Model | |||
ESD Protection Design GUIDELINE | |||
Characteristics Report | |||
Command files | CALIBRE | DRC | |
LVS/XRC/MIPT | |||
QRC | XRC | ||
Std.cell library&IO memory compiler | |||
PDK |
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